1. Field of the Invention
The present invention relates to a data classifier; and more particularly, to a data classifier using fuzzy logic and neural network.
2. Description of Related Art
The advancement of artificial intelligence (AI) has allowed consumers to enjoy electrical products such as robot dogs and personal digital assistants (PDAs) that have their own electronic brain. The electronic brain is formed by many different, smart, powerful, and learnable chips. In order for the electrical products to think and react like a human brain, the chips have to perform a huge amount of complex data calculation in high speed in order to achieve continuous motion and instant reactions.
The speed, size, and robustness of a data classifier are very important because they dictate the performance of the classifier. Non-parametric classification of data is certainly one of the main tasks that let us successfully compare artificial neural networks and fuzzy logic to the conventional methods. Therefore conventional methods require a great amount of computation time in performing relatively complex tasks such as character recognition.
Because of the fuzzy nature of human handwriting, it makes sense to adapt “fuzzy logic” into the data classifier. The “fuzzy logic” control theory is well known in the art of data processing. Rather than evaluating the two values “TRUE” and “FALSE” as in digital logic, fuzzy terms admit to degrees of membership in multiple sets so that fuzzy rules may have a continuous, rather than stepwise, range of truth of possibility. Therefore non-identical handwritten character from same or different users can be approximated using fuzzy logic for fast and robust handwriting recognition. The conventional method of fuzzy recognition relies upon the maximum membership principle. This conventional method is a single factor equation and can only recognize the handwritten character as a whole. Therefore the conventional method is very restricted in terms of speed, robustness, and accuracy.
Generally, analog fuzzy logic is constructed by multi-value logic circuit units, which may be of a voltage type or a current type. For conventional voltage type circuits, operational amplifiers are required for summation or subtraction operations to voltages, which makes the circuit complicated. On the contrary, the current type circuit is capable of proceeding summation and subtraction operations to currents and thus simplifies the circuit and is used in present invention. In addition, the operating speed of a current type circuit is generally higher than that of the voltage type circuit because the gain bandwidth of the operational amplifier restricts the operating speed of the voltage type circuit. Moreover, in a voltage type fuzzy logic circuit, switch capacitors are usually required, which increases the size of a chip for the circuit because a large chip area is required to fabricate a capacitor. The use of switch capacitors also increases the complexity of manufacturing a chip for the circuit as two polysilicon layers are required for fabricating a switch capacitor. The fabrication of a current switch for the current type fuzzy logic can be done by standard digital CMOS technology and thus reduce the complexity of manufacturing a chip for the circuit. Accordingly, the present invention provides a switch current type fuzzy processor for high-speed character recognition.
As a consequence, a high-speed and robust VLSI parallel computation is required to process to complex data such as character recognition. The classifier needs to able to realize different transfer or membership functions such as multiplier, sum, nonlinear, minimum and maximum functions. The input and final output signals of the classifier are digital but the processing and transmitting signals are analog current signals to stimulate high-speed real-time signal processing. The function generator takes digital input from the input buffer and I/O circuit and converts the digital input signals to positive current output and negative current output. The weights of the computation are programmable and the structure of the network is reconfigurable, and so this network can work in multiple-chip mode or can be cascaded in parallel or series to form a large scale network. The programmability and expandability of the classifier is crucial to a high-speed and robust classification of complex data.